Avicena Unveils LightBundleTM, a Chip Interconnect Technology With Dramatically Lower Power Consumption and Higher Bandwidth Density

BERGBLICK, Calif .– () – Avicena Inc., a privately held company based in Mountain View, California, unveiled today Light bundleTM, a highly parallel optical interconnect technology with a range of up to 10 meters for chip-to-chip connections in distributed computing, processor-to-memory disaggregation, and other advanced computing applications. Light bundleTM is based on arrays of novel high-speed GaN microemitters that leverage the micro-LED display manufacturing ecosystem and is fully compatible with high-performance silicon ICs.

Interconnects are becoming the most important bottleneck in computing and network systems. Highly variable workloads are driving the development of closely interconnected, heterogeneous, software-defined clusters of CPUs, graphical processing units (GPUs), data processing units (DPUs) and shared memory blocks. Exploding Artificial Intelligence (AI) and machine learning (ML) workloads exemplify new applications that are driving an increasing need for extremely high-density, low-power, low-latency connections.

About the technology

Today’s high-performance ICs use SerDes-based electrical connections to achieve reasonable IO density. However, the power consumption and bandwidth density of electrical connections decrease rapidly with length. Because optical interconnects do not have these limitations, they have long been the prime contender to replace electrical connections for inter-chip communication. Unfortunately, conventional optical technologies (typically designed for network applications) have been impractical for interprocessor and processor-memory connections because of their low density, high power consumption, inability to tolerate the high operating temperature of ASICs, and high cost.

“All of this is changing with the recent advances in optical emitter technology driven by advances in the display industry,” said Bardia Pezeshki, founder and CEO of Avicena. “We have developed very powerful optical transmitters based on emitter technology from the display industry. These innovative devices would have been impractical just a few years ago. Our optimized devices and materials support 10 Gbit / s connections per lane at temperatures from -40 ° C to +150 ° C with excellent reliability. We refer to our new optical sources as cavity-reinforced optical micro-emitters or CROMEs. We connect CROME arrays to CMOS compatible PDs using multi-core fiber bundles to create massively parallel connections with thousands of parallel lanes over a range of up to 10m. We call this new class of optical connections the Avicena Light bundleTM. ”

Avicena has just demonstrated an array of 200 30μm pitch CROME devices coupled to an array of PDs with a multicore imaging fiber. Individual lanes show excellent performance characteristics up to a data rate of 10 Gbit / s over the entire temperature range from -40 ° C to 150 ° C. This extrapolates to an aggregated link bandwidth of 2 Tbit / s for 200 lanes with a bandwidth density of 10 Tbit / s / mm²2.

The parallelism of the LightBundleTM Technology works well with parallel chiplet interfaces such as AIB, HBI and BoW and can also be used to extend the reach of standard computing connections such as PCIe, NVLink and multi-channel G / DDR memory connections with low power consumption and low latency .

“The cloud and high-performance computing community has long recognized the value of a new class of connectivity,” said Bill Dally, chief scientist at NVIDIA. “Avicena’s technology has the potential to make great improvements in terms of energy efficiency, bandwidth density and range.”

If you want to learn more about Avicena technology, here is a list of upcoming events:

Avicena at OFC 2021:

  • Grace period paper session, Fri. June 11, 8-10 am PDT, B. Pezeshki et al., “Wide and parallel LED-based optical connections with multicore fibers for chip-to-chip communication”

  • Rump session, Wed. June 9, 6 a.m. – 8 a.m. PDT, C. Pfistner, “Slow & Parallel Minimizes Cost & Power”

Avicena cover story in the June 2021 issue of Compound Semiconductor Magazine:

  • Compound Semiconductor, Volume 27, Issue IV 2021, B. Pezeshki et al., “Removing the communication bottleneck from chip to chip by using micro-LED display technology”

About Avicena

Avicena Inc. is a privately held company based in Mountain View, California that specializes in developing next-generation chip-to-chip interconnects that are more energy efficient, offer higher density bandwidth, and support greater range than any current optical or electrical solution. Avicena technology is an important building block in the development of new computing architectures that reduce the energy consumption of our planet.

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